The technical field of radiofrequency signal transmission and reception requires that GSM or DCS devices be provided which can even operate on varying supply voltages, generally between 3V and 5V.
This demand is made today more pressing by the availability of portable telephone sets of the dual band type, which can be operated at both the GSM and DCS frequency standards.
To that aim, it becomes necessary to provide such devices with voltage regulators effective to produce a stable working voltage and capable of accommodating variations in the supply voltage or disturbance of any kind.
Further, to provide electronic devices, integrated monolithically in a single chip, which can operate on signals at frequencies in the GHz range, a technology is required which allows of the integration of components active at very high cut-off frequencies on the order of a few tens of GHz. This involves of necessity the minimization of any parasitic capacitances which, if allowed to appear in the device, could limit the working frequency substantially.
In the instance of circuits integrated with CMOS technology, minimizing the parasitic capacitances is obtained by reducing the thickness of the gate oxide layer of MOS transistors to a minimum. While this can make the transistors extremely fast, it has the disadvantage of lowering their maximum sustainable working voltage; MOS transistors so constructed would exhibit low gate-source or gate-drain breakdown voltages.
In the instance of circuits integrated with bipolar technology, reducing the parasitic capacitances is obtained by reducing the width of the base region as well as the time allowance for the carriers passage through the base region. Here again, the transistor capacity to sustain high working voltages is concurrently reduced; bipolar transistors with this construction would have a low collector-emitter breakdown voltage.
The problem of how to provide GSM-DCS dual band devices operating on varying supply voltages has been addressed by using a combined BiCMOS technology which allows of breakdown voltages up to 3.5V for both bipolar and MOS transistors.
A prior art voltage regulator constructed with BiCMOS/CMOS technology is shown by way of example in FIG. 1 herewith.
This regulator comprises an operational amplifier OPAMP having an output connected to the control terminal of a PMOS transistor M1 to produce a regulated voltage value Vreg.
An input terminal In of the regulator receives a voltage reference Vrif which is applied to the inverting input of the amplifier through a switch controlled by a signal CE (Chip Enable); this signal being a CMOS digital signal arranged to control the turning on/off of the whole device.
The regulated output terminal is fed back to the amplifier inputs through a resistor divider formed of a resistor pair R1, R2. This divider is connected in parallel with an output capacitor C. In essence, upon the occurrence of a variation in the supply, the output voltage value Vreg is fed back to the input of an error amplifier OPAMP at a ratio of R1/(R1+R2) for comparison with a reference voltage Vrif.
The regulated voltage Vreg is given by the following relation: EQU Vreg=Vrif(1+R1/R2)
The output PMOS transistor should be of such dimensions as to ensure operation in the saturation range at the largest delivered current.
In addition, the output capacitor C allows a dominant pole compensation to be carried out and affords good rejection of supply disturbance at all the frequencies.
While being advantageous in many ways, this prior solution has a drawback in that, with the regulator in the "off" state, the voltage Vgd across the gate and drain terminals of the transistor M1 and the voltage Vsd across the source and drain terminals of the transistor M1 are equal to the supply voltage Vpos of the device. Where this voltage Vpos is higher than the gate-drain and source-drain breakdown voltages, the condition becomes unacceptable for the device operation because it would cause the output PMOS transistor M1 to fail.
A viable prior solution to this problem is illustrated schematically by FIG. 2.
Unlike the example of FIG. 1, a cascode structure is shown in FIG. 2, wherein a series of PMOS transistors M1, M2 are employed, with the gate terminal of the transistor M2 being held at a voltage reference Vg2.
This solution has a drawback in that it cannot be applied to low drop regulators, since large-size transistors would be needed which occupy a large circuit area and make compensation difficult from the presence of high parasitic capacitances.
Therefore, until now, no viable solution exits to that can provide a voltage regulator of the low drop type, for construction with BiCMOS/CMOS technology, which has such structural and functional features as to be usable with higher supply voltages than the breakdown voltage of active components, thereby overcoming the limitations of prior art circuits.